Redundant conductor structures for thin film FET driven liquid crystal displays

ABSTRACT

Redundancy is provided in the data and gate lines of the liquid crystal display device for improved reliability and greater fabrication yield. The data lines in particular are preferably fabricated in a multilayer structure with two conductive layers sandwiching a narrow insulating strip. The presence of the insulating strip permits the upper conductive line to be formed without step jumps which can exhibit a tendency for poor electrical connection. The upper and lower conductive layers of the data line are in contact for the length of the lower data line, contact being made on either side of the narrower insulating strip. Similar redundancy, without the necessity of providing an intermediary insulating layer is also provided for the gate lines. The redundancy provided in the present invention is particularly suitable for fabrication methods employed in thin film FET driven LCD devices.

This application is a continuation of application Ser. No. 756,640,filed 7/19/85 now abandoned.

BACKGROUND OF THE INVENTION

The present invention is generally directed to the construction ofliquid crystal display devices. More particularly, the present inventionis directed to redundant conductor structures provided for x and yaddress lines in liquid crystal display (LCD) devices.

A liquid crystal display device typically comprises a pair of flatpanels sealably containing a quantity of liquid crystal material. Theseliquid crystal materials typically fall into two categories: dichroicdyes in a guest/host system or twisted nematic materials. The flatpanels generally possess transparent electrode material disposed ontheir inner surfaces in predetermined patterns. One panel is oftencovered completely by a single transparent "ground plane" electrode. Theopposite panel is configured with an array of transparent electrodes,referred to herein as "pixel" (picture element) electrodes. Thus, thetypical cell in a liquid crystal display includes liquid crystalmaterial disposed between a pixel electrode and a ground electrodeforming, in effect, a capacitor-like structure disposed betweentransparent front and back panels. In general, however, transparency isonly required for one of the two panels and the electrodes disposedthereon.

In operation, the orientation of liquid crystal material is affected byvoltages applied across the electrodes on either side of the liquidcrystal material. Typically, a voltage applied to the pixel electrodeeffects a change in the optical properties of the liquid crystalmaterial. This optical change causes the display of information on theliquid crystal display (LCD) screen. In conventional digital watchdisplays and in newer LCD screens used in miniature televisionreceivers, the visual effect is typically produced by variations inreflected light. However, the utilization of transparent front and backpanels and transparent electrodes also permit the visual effects to beproduced by transmissive effects. These transmissive effects may befacilitated by separately powered light sources for the display,including fluorescent light type devices. LCD display screens may alsobe employed to produce color images through the incorporation of colorfilter mosaics in registration with the pixel electrode array. Some ofthese structures may employ polarizing filters to either enhance orprovide the desired visual effect.

Various electrical mechanisms are employed to sequentially turn on andoff individual pixel elements in an LCD display. For example, metaloxide varistor devices have been employed for this purpose. However, theutilization of thin film semiconductor switch elements is most relevantherein. In particular, a preferable switch element comprises a thin filmfield effect transistor (FET). These devices are preferred in LCDdisplays because of their potentially small size, low power consumption,switching speeds, ease of fabrication, and compatibility withconventional LCD structures.

The pixel elements in an LCD are typically arranged in a rectangulararray of rows and columns. Each pixel electrode is associated with itsown FET switch device. Each switch device is connected to a data lineand a gate line. Electrical signals applied simultaneously to each ofthese lines permit each pixel to be addressed independently.Accordingly, the LCD is typically provided with a set of parallel datalines which can be made to address cells in a horizontal or x direction.Likewise, gate lines are provided for accessing cells in a vertical or ydirection. In operation, the image on the LCD device may be refreshed ata rate which is typically approximately 60 Hz.

More particularly, amorphous silicon FET addressed liquid crystal matrixdisplays provide an attractive approach to high contrast, flat paneltelevision type displays. Ideally, in an FET addressed LCD device, whenthe FET is turned on, the "liquid crystal capacitor" charges to the dataor source line voltage. When the FET is turned off, the data voltage isstored on the liquid crystal capacitor.

Specific attention is now directed to certain problems occurring in LCDdisplay devices which are solved by the practice of the presentinvention. In particular, in thin film FET driven liquid crystaldisplays, the horizontal and vertical address lines (that is, the gatelines and data lines) must all be continuous. For example, in a displayhaving a matrix of 400×400 pixel cells with a resolution of 4 lines permillimeter (100 lines per inch), the total length of the address linesis approximately 100,000 mm. The width of the lines should be less thanapproximately 10 microns in order to maintain a high relative percentageof active cell area in the display. In the fabrication of these devices,defects can occur in many of the processing steps. These defects mayoccur as a result of dust or dirt interfering with metal deposition oradhesion, flaws in photoresist patterns used to etch the metal lines,scratches, etc. Additionally, defects in these lines can result fromunsatisfactory step coverage. This occurs in those situations wheremetal lines are required to traverse a vertical or near vertical sidewall structure, for example, in an etched insulating layer. These stepstypically occur at points in the device at which the horizontal andvertical lines cross over one another. In integrated circuitfabrication, typical open line defect probabilities for lines of thiswidth are of the order of 10⁻⁵ per mm. It is therefore apparent thatmethods for reducing the probability of open x and y addressing linesand methods for enhancing the yield of the LCD device are desired.

SUMMARY OF THE INVENTION

In accordance with a preferred embodiment of the present invention, aliquid crystal display comprises a pair of flat substrates with at leastone of them being transparent. A quantity of liquid crystal material isdisposed and contained between the substrates. An array of pixelelectrodes is disposed on at least one of the substrates. At least oneground plane electrode is disposed on the other of the substrates sothat liquid crystal material is disposed between the pixel electrodesand any ground plane electrodes. Either the array of pixel electrodescomprise transparent material or the ground plane electrode orelectrodes comprise transparent material. In a see-through embodiment ofthe present invention, both substrates, the ground plane electrode, andthe array of pixel electrodes comprise transparent conductive materialsuch as indium tin oxide (ITO). An array of semiconductor switchelements is associated with each pixel electrode. A set of electricallyconductive data lines and a set of electrically conductive gate linesare provided and configured with the switch elements so that voltagesappearing on the data line are applied to select pixel electrodes.

Most relevantly with respect to the present invention, the semiconductorswitch elements preferably comprise thin film field effect transistors.Furthermore, the data lines exhibit a multilayer structure extending forat least a portion of their length with at least two of these layerscomprising conductive material in electrical contact along a portion oftheir length. This structure provides redundancy of up to 90% along thedata line length. In a preferred embodiment of the present invention,the data lines comprise a three layer structure with the intermediatelayer comprising the same insulating material as the gate insulation forthe FET. The first layer of data line metal is preferably deposited atthe same time as the gate metal. Accordingly, this metal pattern isincorporated in the gate metal mask pattern. The second or upperconductive layer comprises metal deposited at the same time as thesource and drain metal for the FET switches. The presence of theinsulating layer and its configuration permit the upper data line layerto be applied without steep step crossovers at the gate lineintersections. Electrical contact is established between the conductivelayers in the data lines on either side of a narrower strip in theinsulating layer. While contact is made along a step structure, thelength of this step is much longer, thereby insuring contact at leastsomewhere along its length. In this way, a redundant data line structureis provided. Similarly, in a preferred embodiment of the presentinvention, redundancy in the gate line layer is also provided. However,in this situation, it is not necessary to employ an intermediaryinsulating layer. It is also noted that the roles of the data lines andgate lines may be reversed by varying electrical connections with theswitch element.

Accordingly, it is an object of the present invention to provide amechanism and structure for redundant gate and data lines in liquidcrystal display devices.

It is also an object of the present invention to provide LCD displaydevices having greater reliability.

Lastly, but not limited hereto, it is an object of the present inventionto provide improved LCD device structure which are readilymanufacturable and which provide improved product yield.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional side elevation view illustrating a thin filmFET;

FIG. 2 is a cross sectional end view illustrating a portion of oneembodiment of the present invention in which a three layer, partiallyredundant data line structure is employed;

FIG. 3A is a plan view illustrating a gate metal pattern employed in apreferred embodiment of the present invention;

FIG. 3B is a plan view illustrating a pattern for gate insulation andactive silicon as part of a thin film FET;

FIG. 3C is a plan view illustrating a metal pattern for source and drainelectrodes and data lines;

FIG. 3D is a plan view illustrating a pattern of pixel electrodematerial in the neighborhood of a thin film semiconductor switch device;

FIG. 4 is a plan view illustrating a portion of an LCD device made inaccordance with the present invention;

FIG. 5 is a plan view showing an enlarged view of a portion of FIG. 5;

FIG. 6 is a schematic diagram illustrating an electrical model for thesemiconductor switch devices associated with each pixel electrode.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates, in cross section, a conventional thin film FET usedin LCD devices. In particular, substrate 20 typically comprises atransparent material such as glass. In accordance with conventionalphotopatterning methods, metal gate electrode 21 is affixed to thissubstrate. A patterned layer of insulating material 24 such as siliconnitride is then typically deposited so as to cover gate electrode 21 andto extend a certain distance on either side thereof. An active layer ofamorphous silicon (α-silicon) is then typically applied and doped withappropriate polarity dopants to produce a channel region wherein currentflow is controlled by electrical signals applied to the gate electrode.In a similar fashion, source and drain electrodes 22 and 23,respectively, are deposited using photopatterning methods to completethe formation of a thin film FET device. It is noted, however, that theopacity of gate material 21 is not a significant viewing limitationsince the gate electrode may only be approximately 10 microns in widthand therefore essentially invisible to the user. In contrast, the pixelelectrodes are by far the larger elements in an LCD device cell. Thepixel electrodes are typically approximately 0.01 inches square.

FIG. 2 is particularly relevant to understanding the present invention.In particular, FIG. 2 is a cross sectional view of a portion of FIG. 5which is more particularly described below. The upper portion of FIG. 2is shown in phantom view since these structures are, strictly speaking,not produced by the mask patterns in FIGS. 3A-3D. These mask patternsare typically employed to generate only one side of the substrates orpanels which form major constituents in an LCD device. As above,substrates 20 and 30 may typically comprise transparent material. Also,as above, ground plane 38 and pixel electrodes 39 are disposed onsubstrates 30 and 20, respectively. These electrodes may comprisetransparent conductive material. Most relevant to the present invention,however, is the data line structure which includes data lines 32 andinsulating material 34. It is seen that the first, conductive layer andthe third, conductive layer, both designated by reference numeral 32 arein electrical contact along either side of narrow insulating strip 34.The first, conductive data line layer is preferably fabricated in thesame process stage as the gate electrodes of the FET switching elements.The second, insulating layer 34 is preferably fabricated in the sameprocess stage as the gate insulating material. The third, conductivelayer in the data line structure is preferably fabricated in the sameprocess stage as the fabrication of the source and drain metallization.The presence of insulating layer 34 permits the third or upperconductive data line layer to cross gate lines, from which it isinsulated, without the formation of step discontinuities which tend todecrease circuit reliability. Furthermore, the first or lowermostconductive line is in contact with the upper conductive line andprovides redundant circuit connection along approximately 90% of thelength of each data line. Lowermost data line 32 is, however, providedwith gaps to accommodate passage of gate line conductors. While itappears that a longer step jump is now required for contact between theconductive layers in the data line, this is in fact not a problem sinceinsulating material strip 34 in FIG. 2 is relatively narrow and sinceelectrical contact is now possible along the entire length of the lowerdata line conductor.

FIGS. 3A-3D are layout patterns employable in the fabrication of thepresent invention. FIG. 3A illustrates a pattern for gate metal andassociated horizontal gate drive lines 31. A scale is provided forreference. Additionally, FIG. 3A illustrates the presence of redundantdata line 32. These lines are redundant in the sense that they do notform a complete electrical circuit in the layer shown but insteadpartially duplicate data line paths which are completed in whole inanother layer as shown in FIG. 3C. Nonetheless, connection is providedto complete the data line circuit, as shown in FIG. 3C. Themetallization layer shown in FIG. 3A is preferably opaque so as toprevent light from reaching the channel regions from one side of thedisplay. The channel regions are formed above the large rectangular areashown in FIG. 3A. Metallic pad 36 is also shown in the layer illustratedin FIG. 3A. Pad 36 facilitates electrical connection between the devicedrain and the pixel electrode.

After the metallization layer of FIG. 3A is formed on an opaquesubstrate or on a transparent substrate such as glass, the pattern ofFIG. 3B is employed in the deposition of insulating and semiconductinglayers. In particular, a layer of silicon nitride or other insulatingmaterial is deposited in the pattern shown in FIG. 3B. The insulatingmaterial pattern shown in FIG. 3B serves several purposes. Firstly, thispattern provides gate insulating material for thin film FET devices.Secondly, this insulating layer is disposed so as to electricallyinsulate the gate lines from the data lines. Lastly, it is noted thatthe vertical portions extending upwardly and downwardly from the centralpatch region of FIG. 3B overlie data lines 32 shown in FIG. 3A. However,it is noted that the insulating layer in FIG. 3B is narrower than dataline 32 in FIG. 3A. This permits the formation of a partially redundantdata line as shown in FIG. 3C. Because the width of insulating layer 34in FIG. 3B is narrower, electrical contact is thereby permitted betweenthe data line conductors shown in FIGS. 3A and the complete data lineconductors shown in FIG. 4C, both of which are indicated by referencenumeral 32. FIG. 2 provides a cross sectional view of the resultingstructure.

As pointed out above, the pattern of FIG. 3B is employed to serve anadditional function. In particular, it serves as a pattern for thedeposition of a layer or layers of semiconductor material. Inparticular, it is preferable to employ a triple layer having the patternshown in FIG. 3B. In this case, the lowermost (that is, first) layercomprises silicon nitride, the next layer comprises α-silicon, and thenext layer comprises α-silicon doped with material so as to provide thelayer with an N⁺ polarity. These layers are formed using conventionalthin film FET processing.

The next layer applied to the substrate is a metallization layer havingthe configuration illustrated in FIG. 3C. In particular, the fingerprojections 32a and 32b extend from data line 32. These projections formsource electrodes for an FET. Metallization pattern 33 provides a commondrain electrode for the FET formed. This drain electrode is ultimatelyconnected to pixel electrode 39 shown in FIGS. 2, 6, and 3D. It is alsoin electrical contact with pad 36 in FIG. 3A. Data line 32 is connectedto source electrodes 32a and 32b and in addition, because of thenarrower width of insulating layer of FIG. 3B, data line 32 is incontact with the partially redundant data line having the same referencenumeral in the layer of FIG. 3A. This provides a redundant structure forincreased display reliability. It is also noted that gate line 31 isprovided with enhanced metallization from the layer of FIG. 3C, again toprovide enhanced display reliability.

The next layer to be applied is the layer of pixel electrode patterns.The pixel electrodes must necessarily comprise electrically conductivematerial. However, depending upon the specific nature of the LCD device,the electrically conductive material may or may not be transparent.However, for transparency, indium tin oxide is preferably employed forthis purpose. Accordingly, although pixel electrodes 39 compriseelectrically conductive material, they are hatched as glass in figuresherein to suggest their potentially transparent nature. It is, ofcourse, required that either the ground plane electrodes or the pixelelectrodes, or both, comprise transparent material. If they are bothopaque, the purpose of the display is defeated. With further referenceto the pixel electrodes, it is noted that FIG. 3D illustrates thepresence of four such pixel electrodes. However, the semiconductorswitch is in fact associated with the pixel electrode 39 in the lowerrighthand corner of FIG. 3D. This pixel electrode is in electricalcontact with metal (drain) pad 33 in FIG. 3C.

FIG. 4 illustrates in an enlarged view, a single pixel cell and portionsof the cells which surround it. The gate lines associated with the cellsare shown extending in a horizontal direction. The data lines associatedwith the cells are shown extending in a vertical direction. It is noted,however, that the relative directionality of these lines is not fixedand that alternate configurations may be employed in which thehorizontal and vertical roles are reversed. Additionally, each pixelcell is seen to be uniquely associated with a selected data line andgate line. Each pixel cell is seen to include a pixel electrode and itsassociated semiconductor switching device. The structure seen in FIG. 4typically comprises one side of a liquid crystal display device. Theother side typically comprises a ground plane electrode disposed on atransparent substrate. Liquid crystal material is disposed between thepixel electrodes and the ground plane electrode or electrodes. While thepixel cells shown in FIG. 4 are square, it is also possible to employcells of differing shapes or varying sizes. Likewise, while the datalines and gate lines are shown extending in horizontal and verticaldirections, it is also possible to employ data lines disposed so as tomore closely resemble oblique coordinate systems.

FIG. 5 provides a detailed view of the structure that results from thefabrication steps performed using the patterns shown in FIGS. 4A-4D.FIG. 5 provides an overview of the resulting structure and serves tomore particularly describe interlayer structural relationships. FIG. 5is also notable for the presence of section line 2 referringparticularly to FIG. 2 which show the cross section of a typical dataline.

FIG. 6 provides an electrical schematic diagram for a single pixel cell.In particular, a capacitor symbol with upper plate 39 and lower plate 38is employed to represent and suggest the capacitor portion of the cell.Lower plate 38 typically comprises the ground plane electrode and upperplate 39 typically comprises the individual pixel electrodes. The pixelelectrodes are electrically connected to drains 33 of FET with gate 31and source electrodes 32a and 32b. The gate lines and data lines are asshown in FIG. 6. It should be noted, however, that references herein tosource and drain electrodes are exemplary only. As is well known in theart, FET devices often exhibit symmetries in which source and draindesignations exist only for convenience or as a result of externaldevice connections.

It is also possible to fabricate liquid crystal display devices whichdisplay color images rather than monochrome ones. In such devices, amosaic color filter is typically employed. This color filter ispreferably disposed over the ground plane electrode. In accordance withthe present invention, it is also possible to dispose spacer material onthis filter. However, this is a less desirable arrangement for thereason that the color filter layer must be accurately registered andaligned with respect to the thin film transistor array and theassociated pixel electrodes.

As indicated above, different forms of liquid crystal material may beemployed in the present invention. In the event that twisted nematicmaterials are employed, a pair of polarizers are also required. Thesepolarizers are typically disposed external to the walls of the LCDdevice which contain the liquid crystal material. In LCD devicesemploying dichroic dyes (guest/host systems), polarizer pairs are nolonger required. In these embodiments, systems with either a singlepolarizer or no polarizers at all may be employed.

Accordingly, from the above, it may be appreciated that the liquidcrystal display device of the present invention provides improveddisplay performance, manufacturing yield and is compatible withconventionally employed LCD device fabrication methods. It is also seenthat the present invention facilitates the formation of complete, highquality, high contrast images, even color images.

While the invention has been described in detail herein in accord withcertain preferred embodiments thereof, many modifications and changestherein may be effected by those skilled in the art. Accordingly, it isintended by the appended claims to cover all such modifications andchanges as fall within the true spirit and scope of the invention.

The invention claimed is:
 1. A liquid crystal display comprising:a pairof flat substrates, at least one of which is transparent; a quantity ofliquid crystal material disposed and contained between said substrates;an array of pixel electrodes disposed on at least one of saidsubstrates; at least one ground plane electrode disposed on the otherone of said substrates, so that liquid crystal material is disposedbetween said pixel electrodes and any of said ground plane electrodes,with at least one of said ground electrodes and said array of pixelelectrodes being transparent; an array of thin film field effecttransistor switch elements associated with said pixel electrodes; a setof electrically conductive data lines, said data lines having amultilayer structure including an insulative layer, said multilayerstructure extending for at least a portion of the length of said datalines, with at least two of these layers comprising conductive materialdisposed above and below said insulative layer and in electrical contactalong a portion of the length of said data lines; and a set ofelectrically conductive gate lines, said switch elements, said datalines and said gate lines being electrically connected so as to permitvoltages appearing on said data lines to be applied to select pixelelectrodes in accordance with signals present on said gate lines, saidgate lines and said data lines being insulated from one another by meansof said insulative layer in said multilayer data lines, said multilayerinsulative layer extending across said gate lines so that data lineconductors cross said gate lines without traversing substantiallyvertical step discontinuities.
 2. The display of claim 1 in which saidswitch elements include a gate metal layer, a gate insulating layer anddistinct source and drain patterns in a metal layer overlying said gateinsulation layer.
 3. The display of claim 2 in which said multilayerstructure includes three layers.
 4. The display of claim 3 in which saiddata lines include a first, conductive layer disposed in the same layeras said gate metal.
 5. The display of claim 4 in which said first dataline layer includes gaps through which said gate lines pass.
 6. Thedisplay of claim 5 in which said data lines include a second, insulatinglayer disposed in the same layer as said gate insulation.
 7. The displayof claim 1 in which said data lines include a third, substantiallycontinuous, conductive layer disposed over said insulating layer.
 8. Thedisplay of claim 6 in which said data lines include a third,substantially continuous, conductive layer disposed in the same layer assaid source and drain metal patterns.
 9. The display of claim 1 in whichsaid electrical contact is made on either side of said insulation layer.10. The display of claim 1 in which said gate lines include first andsecond conductive layers.
 11. The display of claim 2 in which said gatelines comprise conductive material in .[.said.]. .Iadd.a .Iaddend.firstlayer thereof lying in the same layer as said gate metal with .[.said.]..Iadd.a .Iaddend.second layer .Iadd.of .Iaddend.conductive materialapplied in the same layer as said source and drain patterns.
 12. Thedisplay of claim 11 in which said second layer of said gate linesinclude gaps through which said data lines pass.
 13. The display ofclaim 11 in which said first layer of said gate lines is substantiallycontinuous.
 14. The display of claim 1 in which said electricallyconductive gate lines, said switch elements, and said data lines areelectrically connected so as to reverse the roles of said gate lines andsaid data lines with respect to their extending in horizontal andvertical directions.
 15. The display of claim 1 in which said switchelements comprise amorphous silicon field effect transistors.
 16. Aliquid crystal display comprising:a pair of flat substrates, at leastone of which is transparent; a quantity of liquid crystal materialdisposed and contained between said substrates; an array of pixelelectrodes disposed on said at least one substrate; at least one groundplane electrode disposed on the other of said substrates, so that liquidcrystal material is disposed between said pixel electrodes and saidground plane electrode said ground plane electrode and said array ofpixel electrodes being transparent; an array of thin film field effecttransistor switch elements associated with said pixel electrodes, saidtransistor switch elements including source and drain electrodes with atleast one of said electrodes exhibiting multiple finger projections; aset of electrically conductive data lines said data lines having amultilayer structure including an insulative layer, said multilayerstructure extending for at least a portion of the length of said datalines; and a set of electrically conductive gate lines, said switchelements, said data lines and said gate lines being electricallyconnected to permit voltages appearing on said data lines to be appliedto said pixel electrodes in accordance .Iadd.with .Iaddend.signalspresent on said gate lines said gate lines and said data lines beinginsulated from one another by means of said insulative layer, saidinsulative layer extending across said gate lines so that said datalines cross said gate lines without transversing substantially verticalstep discontinuities.
 17. The display of claim 16 in which said thinfilm field effect transistor switch elements include amorphous silicontransistors.
 18. A liquid crystal display comprising:a pair of flatsubstrates, at least one of which is transparent; a quantity of liquidcrystal material disposed and contained between said substrates; anarray of pixel electrodes disposed on at least one of said substrate; atleast one ground plane electrode disposed on the other one of saidsubstrates, so that liquid crystal material is disposed between saidpixel electrodes and said ground plane electrodes, with at least one ofsaid ground plane electrodes and said array of pixel electrodes beingtransparent; an array of thin film field effect transistor switchelements associated with said pixel electrodes, said transistor switchelements having source and drain electrodes with at least one of saidelectrodes exhibiting multiple projections; a set of electricallyconductive data lines, said data lines having a multilayer structureincluding an insulative layer, said multilayer structure extending forat least a portion of the length of said data lines with at least two ofsaid layers comprising conductive material in electrical contact along aportion of the lengths of said data lines; and a set of electricallyconductive gate lines, said switch elements, said data lines and saidgate lines being electrically connected so as to permit voltagesappearing on said data lines to be applied to select pixel electrodes inaccordance with signals present on said gate lines, said gate lines andsaid data lines being insulated from one another by means of saidinsulative layer in said multilayer data lines, said multilayerinsulative layer extending across said gate lines so that data lineconductors cross said gate lines without traversing substantiallyvertical step discontinuities.
 19. The display of claim 18 in which saidswitch elements include a gate metal layer, a gate insulation layer anddistinct source and drain patterns in a metal layer overlying said gateinsulation layer.
 20. The display of claim .[.1.]. .Iadd.19 .Iaddend.inwhich said multilayer structure includes three layers.
 21. The displayof claim 20 in which said data lines include a first, conductive layerdisposed in the same layer as said gate metal.
 22. The display of claim21 in which said first data line layer includes gaps through which saidgate lines pass.
 23. The display of claim 22 in which said data linesinclude a second, insulative layer disposed in the same layer as saidgate insulation.
 24. The display of claim 23 in which said secondinsulative layer extends across said gate lines, whereby additional dataline conductor lines cross said gate lines without traversing verticalstep jumps.
 25. The display of claim 24 in which .[.daid.]. .Iadd.said.Iaddend.data lines include a third, substantially continuous,conductive layer disposed over said second, insulative layer.
 26. Thedisplay of claim 24 in which said data lines include a third,substantially continuous, conductive layer disposed in the same layer assaid source and drain metal patterns.
 27. The display of claim 24 inwhich said data lines include a third, substantially continuous,conductive layer in contact with said first, conductive layer.
 28. Thedisplay of claim 27 in which said contact is made on either side of saidinsulation layer.
 29. The display of claim .[.18.]. .Iadd.19 .Iaddend.inwhich said gate lines include first and second conductive layers. 30.The display of claim 29 in which said gate lines comprise conductivematerial in said first layer thereof lying in the same layer as saidgate metal with said second layer conductive material applied in thesame layer as said source and drain patterns.
 31. The display of claim30 in which said second layer of said gate lines includes gaps throughwhich said data lines pass.
 32. The display of claim 30 in which saidfirst layer of said gate lines is substantially continuous.
 33. Thedisplay of claim 18 in which said electrically conductive gate lines,said switch elements and said data lines are electrically connected soas to reverse the roles of said gate lines and said data lines withrespect to their extending in horizontal and vertical directions. 34.The display of claim 18 in which said switch elements comprise amorphoussilicon field effect transistors. .Iadd.
 35. A liquid crystal display,comprising:a plurality of pixel cells arranged substantially in rows andcolumns; a plurality of switch element means for turning on and offindividual pixel cells, each switch element means having aninterdigitated electrode structure and each coupled to a different oneof said plurality of pixel cells; a plurality of electrically conductivedata lines, each of said data lines having a multilayer structure; and aplurality of electrically conductive gate lines; said switch elementmeans, said data lines and said gate lines being electrically connectedto permit voltages appearing on said data lines to be applied toselected pixel cells in accordance with signals present on said gatelines. .Iaddend. .Iadd.
 36. The liquid crystal display of claim 35wherein each of said switching element means is a thin-film field effecttransistor having at least one layer of semiconductor material..Iaddend. .Iadd.37. The liquid crystal display of claim 36 wherein saidat least one layer of semiconductor material is amorphous silicon..Iaddend. .Iadd.38. The liquid crystal display of claim 37, wherein eachof said field effect transistors comprises:a gate electrode connected toat least one gate line of said plurality of gate lines; a sourceelectrode connected to at least one data line of said plurality of datalines; and a drain electrode connected to one of said plurality of pixelcells; at least one of said source electrode and said drain electrodehaving multiple finger projections disposed adjacent at least one fingerprojection of another of said source and drain electrodes to form saidinterdigitated electrode structure. .Iaddend. .Iadd.39. The liquidcrystal display of claim 35 wherein each of said plurality of data linescomprises:a first layer of conductive material disposed in the samelayer as said gate lines with gaps; a layer of insulation materialdisposed over said first layer; and a second layer of conductivematerial disposed over said insulation layer and in contact with saidfirst conductive layer along at least a portion of said data line, eachdata line second layer extending across each gate line and spacedtherefrom by said insulation layer without traversing substantiallyvertical step discontinuities. .Iaddend. .Iadd.40. The liquid crystaldisplay of claim 35 wherein each of said gate lines have a multilayerstructure. .Iaddend. .Iadd.41. A liquid crystal display, comprising:aplurality of pixel cells arranged substantially in rows and columns; aplurality of switch element means for turning on and off individualpixel cells, each switch element means having an interdigitatedelectrode structure and each coupled to a different one of saidplurality of pixel cells; a plurality of electrically conductive datalines; and a plurality of electrically conductive gate lines whereineach of said plurality of gate lines comprises:a first layer ofconductive material; a layer of insulation material disposed over saidfirst layer; and a second layer of conductive material disposed oversaid insulation layer and in contact with said first conductive layeralong at least a portion of said gate line, each gate line secondconductive layer having gaps therein through which said data lines pass;said switch element means, said data lines and said gate lines beingelectrically connected to permit voltages appearing on said data linesto be applied to selected pixel cells in accordance with signals presenton said gate lines. .Iaddend. .Iadd.42. The liquid crystal display ofclaim 41 wherein each of said switching element means is a thin-filmfield effect transistor having at least one layer of semiconductormaterial. .Iaddend. .Iadd.43. The liquid crystal display of claim 42wherein said at least one layer of semiconductor material is amorphoussilicon. .Iaddend. .Iadd.44. The liquid crystal display of claim 43wherein each of said field effect transistors comprises:a gate electrodeconnected to at least one gate line of said plurality of gate lines; asource electrode connected to at least one data line of said pluralityof data lines; and a drain electrode connected to one of said pluralityof pixel cells; at least one of said source electrode and said drainelectrode having multiple finger projections disposed adjacent at leastone finger projection of another of said source and drain electrodes toform said interdigitated electrode structure. .Iaddend. .Iadd.45. Aliquid crystal display, comprising:a plurality of pixel cells arrangedsubstantially in rows and columns; a plurality of switch element means,each coupled to a different one of said plurality of pixel cells; eachof said switch element means comprising a thin-film field effecttransistor having at least one layer of semiconductor material and aninterdigitated electrode structure; a plurality of electricallyconductive data lines, each having a multilayer structure; and aplurality of electrically conductive gate lines; said switch elementmeans, said data lines and said gate lines being electrically connectedto permit voltages appearing on said data lines to be applied to selectpixel cells in accordance with signals present on said gate lines..Iaddend. .Iadd.46. The liquid crystal display of claim 45 wherein saidat least one layer of semiconductor material is amorphous silicon..Iaddend. .Iadd.47. The liquid crystal display of claim 46, wherein eachof said field effect transistors comprises:a gate electrode connected toat least one gate line of said plurality of gate lines; a sourceelectrode connected to at least one data line of said plurality of datalines; and a drain electrode connected to one of said plurality of pixelcells; at least one of said source electrode and said drain electrodehaving multiple finger projections disposed adjacent at least one fingerprojection of another of said source and drain electrodes to form saidinterdigitated electrode structure. .Iaddend. .Iadd.48. The liquidcrystal display of claim 45, wherein each of said plurality of datalines comprises: first layer of conductive material disposed in the samelayer as said gate lines with gaps; a layer of insulation materialdisposed over said first layer; and a second layer of conductivematerial disposed over said insulation layer and in contact with saidfirst conductive layer along at least a portion of said data line, eachdata line second conductive layer extending across each gate line andspaced therefrom by said insulation layer without traversingsubstantially vertical step discontinuities. .Iaddend. .Iadd. The liquidcrystal display of claim 45 wherein each of said gate lines has amultilayer structure. .Iaddend. .Iadd.50. The liquid crystal display ofclaim 49, wherein each of said plurality of gate lines comprises:a firstlayer of conductive material; a layer of insulation material disposedover said first layer; and a second layer of conductive materialdisposed over said insulation layer and in contact with said firstconductive layer along at least a portion of said gate line, each gateline second conductive layer having gaps therein through which said datalines pass. .Iaddend. .Iadd.51. A liquid crystal display, comprising: aplurality of pixel cells arranged substantially in rows and columns; aplurality of thin-film field effect transistors, each having aninterdigitated electrode structure and each coupled to a different oneof said plurality of pixel cells to apply a voltage to said one pixelcell; a plurality of electrically conductive data lines, each having amultilayer structure; and a plurality of electrically conductive gatelines; said field effect transistors, said data lines and said gatelines being electrically connected to permit voltages appearing on saiddata lines to be applied to select pixel cells in accordance withsignals present on said gate lines. .Iaddend. .Iadd.52. The liquidcrystal display of claim 51 wherein each of said field effecttransistors comprises at least one layer of semiconductor material..Iaddend. .Iadd.53. The liquid crystal display of claim 52 wherein saidat least one layer of semiconductor material is amorphous silicon..Iaddend. .Iadd.54. The liquid crystal display of claim 51 wherein eachof said gate lines has a multilayer structure. .Iaddend. .Iadd.55. Theliquid crystal display of claim 51, wherein each of said plurality ofdata lines comprises:first layer of conductive material disposed in thesame layer as said gate lines with gaps; a layer of insulation materialdisposed over said first layer; and a second layer of conductivematerial disposed over said insulation layer and in contact with saidfirst conductive layer along at least a portion of said data line, eachdata line second conductive layer extending across each gate line andspaced therefrom by said insulation layer without traversingsubstantially vertical step discontinuities. .Iaddend. .Iadd.56. Theliquid crystal display of claim 51, wherein each of said plurality ofgate lines comprises: a first layer of conductive material; a layer ofinsulation material disposed over said first layer; and a second layerof conductive material disposed over said insulation layer and incontact with said first conductive layer along at least a portion ofsaid gate line, each gate line second conductive layer having gapstherein through which said data lines pass. .Iaddend.